Samsung unveils zHBM and zNAND-O 3D memory concepts, 400+ layer V10 NAND in production

At the Future of Memory and Storage (FMS) 2026 conference in Santa Clara, Samsung laid out an aggressive AI-memory roadmap. It introduced concept architectures zHBM (Z-axis High Bandwidth Memory) and zNAND-O, claiming up to 8x higher speed and 10x greater density versus HBM5 — a long-horizon vision aimed squarely at the memory-bandwidth bottleneck that increasingly constrains large-model training and inference.

On the nearer-term production side, Samsung showed a V10 BV-NAND prototype featuring 400+ layers built with wafer-bonding, delivering 58% higher density than the prior V9 generation. The company plans to ramp HBM4 in the second half of 2026, positioning zHBM as a post-2028 offering that would arrive alongside HBM5. This cadence keeps Samsung in direct competition with SK Hynix and Micron for the AI-memory supply that hyperscalers and chipmakers are desperate to lock down.

The announcement matters because memory, not just compute, is a gating factor for AI infrastructure — and it ties into the week's broader hardware theme, where Anthropic is building custom chips, AMD acquired Taalas to etch models into silicon, and NVIDIA continues its stack dominance. Higher-bandwidth, higher-density memory directly improves the economics of serving trillion-parameter MoE models like Qwen3.8-Max.

The caveats are the usual for concept announcements: zHBM and zNAND-O are architectural visions with post-2028 timelines, not shipping products, and Samsung's speed/density multipliers are vendor claims without independent validation. The concrete near-term signal is the 400+ layer V10 NAND prototype and the H2 2026 HBM4 ramp — those are the milestones that actually affect AI infrastructure buyers in the next year. For now, Samsung is planting a flag on the long-term memory roadmap while competing on this generation's HBM supply.